Power Factor Correction Analysis And Optimization Design Of The Chip

With the wide development of the electronic equipment, people draw attention of the harmonic pollution. Power Factor Correction is an effective technique for reducing harmonic pollution. And Power actor Correction can increasing the efficiency of the electrical energy. By the power factor correction, the input current is proportional to the input voltage. PFC is classified as the passive PFC and the active PFC. The active PFC is widely used now.The conventional PFC topology is constituted by Boost circuit. But in the boost circuit electrical isolation is hard to achieve between the input and output. In this paper the circuit of Sepic-PFC is introduced. In the Sepic-PFC electrical isolation is easy to achieve between the input and the output. The conventional Sepic-PFC circuit has its disadvantages. Therefore, the modified Sepic-PFC topology is introduced in this paper. The topology is the bridgeless PFC and the Sepic converter with soft-switching feature. The principle of Sepic converter and the signal model of Sepic converter are researched. The simulations in detail of the converter are carried out. The basic principles and main frames of its internal modules are analyzed. The modules contain VEA, oscillator, comparator and so on. According to the analysis above, the design method and results are given. Experimental results verify that analysis and simulation results are correct. Power Factor Correction can increase the efficiency of the electrical energy and reduce harmonic pollution.