Research And Design Of Virtual Logic Analyzer Card

With the rapid development of the IC industry, the trend of ASIC developmentbecomes systematical, and its function has become more powerful. Accordingly, thetest problem becomes more complex in the digital domain，and all the globalmanufacturers of measuring instrument are dedicating to the study of this problem.The logic analyzer is an essential tool in the digital domain measurement instrument,and it has been leading the trend of the development of digital measuring instrument.Currently, the price of the logic analyzer is high on the domestic and foreign markets,and it is difficult for average users to buy, so it is necessary to research and design afull-featured, lower production cost logic analyzer to meet the needs of students.Currently, the high operating frequency, large data storage capacity,multifunction and network become the development trend of logic analyzer. Firstly,giving a detailed description of the development status of foreign logic analyzer, anddescribing the development status of the domestic logic analyzer, then giving them acomparison. Secondly, introducing the basic working principle of the logic analyzerfrom timing sampling rate, state analysis rate to data storage, and explaining thelogic analyzer core content—trigger circuit in detail. The flexible trigger ensureslogic analyzer can capture a variety of circuit data quickly and accurately in differentconditions. The difficulty of designing logic analyzer is the triggering circuit, and itis also the key link to improve the performance of the logic analyzer.After the analysis and comparison of the current mainstream logic analyzerperformance, a reasonable performance indicator has been submitted according tostudent’s learning needs: Designing a virtual logic analyzer card working with thecomputer platform. It has two operation modes: the logic State Analyzer and thelogic Timing Analyzer;16signal sampling channels and two external clock channels;the maximum timed sampling rates is100MHz and the Maximum state rate is30MHz; with SRAM (Static Random Access Memory) memory chips, each signalchannels storage capacity is1Mbit,16channels’ is16Mbit; with several trigger modes: Word trigger, Delay trigger, Sequence trigger, Glitch trigger etc. The designof the hardware architecture uses the FPGA+MCU+USB model, and the FPGAincludes trigger circuit and data storage control circuit, the data communicatebetween USB and PC under MCU control. FPGA and MCU work with SLAVEFIFO mode, two SRAMS realize data cache.Realizing high-speed data exchange between PC and USB through settingdifferent register parameter with C language programming in MCU; Realizing avariety of trigger conditions and the data storage control with Verilog HDL languageprogramming in FPGA; Realizing the sampled data analysis, display and the virtuallogic analyzer card’s setting with LabVIEW language programming in PC.Drawing the virtual logic analyzer card’s schematic, and converting to PCBcircuit layout with Protel99SE software. Placing the components and wiring thesignal reasonably with high speed circuit PCB knowledge, and processing theproblems of power and ground.Finally, the reasonable suggestion for improvement is put forward according tothe deficiencies in circuit design.