The Design And Implementation Of A Multi-channel Dbf Special Test Simulator

In recent years, some new theory, new techniques and new devices have been used in radar systems,the radar technology has entered a new stage of development.The digital array technology is one of the most important new techniques.It is a fully digital array radar that using the technique of digital beam forming (DBF) on both of the receive and transmit beam forming.During the course of developing and debugging DBF processor of digital array radar, it is difficult to test the radar’s performance and indicators in a completely real environment, so the development of echo signal simulator of digital array radar has become an inevitable. In this paper,the simulator which is designed for a large array DBF processor is designed using FPGA+PC software and taking9channels of2.5Gbps fibers as the transmission channels. The PC software witch is written by MFC is mainly responsible to send various commands to the FPGA, and set the space information of targets and interferences.and then, in accordance with certain processes,to test and display the performance of the beampatterns witch is formed by the DBF processor returned by the DBF processor. The FPGA portion is mainly responsible to analog the echo signal of targets, interferences and noise depand on the information transmitted from the PC software and transmit the signals to the DBF processor by the given frame format,and then receive the results from the DBF processor to send to the host computer.The test resulte shows that the simulator has achieved the functionality required by the system, at the same time it verify that the DBF processor has met the design requirements.