Research Of Bayer Pattern Demosaicking Algorithm And Hardware Implementation

Demosaicking, one of the most important parts in the image signal processing pipeline, is widely used in image acquisition systems. With the development of the semiconductor manufacturing technology, higher complexity algorithms can be implemented on chip. The past low complexity and low performance demosaicking algorithm can not meet consumers’requirement. On the other hand, high performance algorithms cost too much resourse to implementing in hardware. In this paper, a low cost and high performance demosaicking algorithms is proposed. The corresponding hardware is designed.In the proposed method, improved direction detectors are firstly derived from the CFA (Color Filter Array) information to produce an initial edge orientation map. Then the initial edge orientation map is passed through a cross-shape median filter to remove most isolated wrong directions. A statistical analysis is also performed in the filtered edge orientation map to decide the interpolation directions for pixels locates in the regions of fine texture or at the borders of adjacent edges. Further, a refine step is included to reduce the interpolation color artifacts. Experimental results confirm that the proposed algorithm performs better compared to several classic and concurrent techniques, both subjectively and objectively. The proposed method provides a good compromise between image quality and computational cost.Hardware for the proposed algorithm is designed. Green buffer is used to solve the inter-color data dependent problem. The hardware cost of green interpolation engine is reduced by70%through reusing computing cores and former computing results. The throughput can achieve1full-resolution pixel/cycle.