Low Noise PLL Design

At present, frequency synthesizers applied in wireless microphones and wirelessradios are all imported, and, there are no VCO (Voltage-Controlled Oscillator) and LPF(Low Pass Filter) in those Phase Lock Loops (PLL), which makes circuit design morecomplicated. A fully integrated low-noise phase-locked loop is designed for wirelessaudio transmission in the paper, which analyzes the relationship of phase noise in thePLL and the contribution of various noise sources to the overall noise.The PLL circuit includes phase frequency detector (PFD), charge pump (CP), loopfilter (LPF), voltage-controlled oscillator (VCO), and divider. In order to get a lowphase noise, a Bonding wire inductor and2nd harmonic filter are employed involtage-controlled oscillator. The work frequency of VCO is from1GHz to2GHz, andit is divided by CML divide-by-2or CML divide-by-4to get output signal from250MHz to1GHz. And in addition to loop filter, the PLL system also has an input pinwhich can be used to modulate VCO for external signal such as voice. Therefore, thePLL system can also be used as a transmitter with an external power amplifier (PA).Furthermore, we also use a new technique to reduce the capacitance of loop filter toone tenth to save silicon area. Then, this PLL system is designed and simulated usingGlobal Foundry0.35um2p3m3V dual gate CMOS process. At last, the PLL systemtape out in Global Foundry0.35um2p4m3V/5V dual gate CMOS MPW technology,and its test results agree well with simulation results.