Study On Electrical Characteristics Of High-k NdAlO₃/SiO₂Stack Gate In MIS Structure

As the scaling of MOSFETs follows Moore’s law, high-k material as gate dielectricbecomes an inevitable trend to ensure the high driving force of semiconductor devicesand restrain the gate leakage current. In order to obtain a new high-k material which canperfectly replace traditional SiO₂gate dielectric, various attempt and research has beendone. The stack structure combining NdAlO₃which possesses high thermal stabilitywith SiO₂interfacial layer is studied in this thesis, which can compatible withconventional silicon process and reduce the interface defects between gate dielectric andsubstrate.The atomic layer deposition process which is used to fabricate NdAlO₃isdiscussed firstly. After optimizing the process parameters of Nd2O₃, Al2O₃, and thepulsing ratio of them, the NdAlO₃material with a certain stoichiometry is depositedsuccessfully.The C-V curve which is often used to evaluate the quality of gate dielectric in theprocess of optimizing the deposition parameters is analyzed, and the impact on whichthe metal-semiconductor work function difference and gate dielectric defects have isdiscussed. The flatband voltage hysteresis between forward and backward C-V curve,midgap voltage shift and the impact of interface traps on high frequency curve iscalculated by contracting measured and standard C-V curve. It is concluded that high-kgate NdAlO₃stack with SiO₂interfacial layer has low dielectric traps, fixed charges andperfect interface between silicon and insulator.The impact of annealing on NdAlO₃gate dielectric material is investigated. Theresult shows that NdAlO₃is still amorphous, its dielectric constant is improved and thegate leakage current is reduced after annealing at950℃. The FP emission of the gateleakage current transport mechanism which is affected by electric field and temperatureis focused on. The characteristics and relationships in internal electric field of high-kgate and SiO₂interfacial layer in the stack structure is induced theoretically, and theinfluce of gate voltage stress on leakage current is analyzed.