Realization Of High-κ Gate Stack MIS Structure And Performance Enhancement Technology Research

Scaling transistor’s dimensions has been the main tool to power the development ofsilicon integrated circuits （ICs）. An equivalent gate oxide thickness （EOT） of1nm hasbeen used for the sub-45nm Si complementary metal oxide semiconductor （CMOS）process. As we know, when EOT is thinned to1nm, its physical thickness correspondsto only4-5atom layers, leading to the limited extendability of SiO₂as the gatedielectric. Because of issues such as process controllability, high leakage current and thedemands of the downscaling of an MOSFETS, a thicker film with a higher dielectricconstant is required to reduce the leakage current while maintaining the same gatecapacitance. To integrate the high-κ gate dielectric for CMOS process is only way tomeet these problems. These high dielectric constant materials can suppress the gateleakage current, at least for direct quantum mechanical tunneling, which exponentiallydepends upon the dielectric thickness. However, due to the reliability issues of high-κmaterials, TSMC firstly integrated it in the December of2011since the Intel firstlyintegrated high-κ/Metal gate technology in their CMOS fabrication process in2007.Therefore, the most popular high-κ materials such as HfO₂or Hf-based gate materialsneed to be further investigated. In this paper, the characteristic of Hf-based gate materialand MOS devices used HfO₂film as gate dielectric are researched systematically, andthe author’s major contributions are outlined at follows:1. Effects of the ALD deposition conditions on the properties of the HfO₂/SiO₂.Based on the ALD deposition experiments, the main factors such as O3concentration,deposition temperature and oxidants, which has an effect on the characteristic ofHf-based gate dielectric were investigated. The experiment results indicate that the O3concentration and deposition temperature affected the residual, stoichiometric,permittivity and electrical properties of HfO₂films seriously owing to its affectedwherther the saturation ALD reaction occurs. Meanwhile, the films deposited usingdifferent oxidants （H2O and O3） also present a significiant difference in physical andelectrical properties due to its different reaction mechanism.2. Effects of thermal treatments on the physical and electrical characteristic ofHfO₂/SiO₂gate stack. After as-deposited H2O-based and O3-based ALD HfO₂/SiO₂gatestack were annealed with a compatible gate-last annealing process in N2,the surfaceroughness, film thickness, impurity, stoichiometric and valence band offset of theHfO₂/SiO₂gate stack were measured and discussed. Furthermore, the HfO₂/SiO₂gate stack MOS capacitor were also fabricated and its electrical testing results show that theflat band voltage（VFB） of the H2O-based and O3-based HfO₂/SiO₂gate stack shifts todifferent directions after annealing because of the interface dipoles. The further I-Vtesting results indicat that both of the H2O-based and O3-based HfO₂/SiO₂gate stackMOS capacitor’s gate leakage current are less than2x10-9nA when Vgis2V, and itdecrease to1x10-9nA after annealing. The main leakage mechanism for the HfO₂/SiO₂gate stack MOS capacitor is Schottky emission.3. Characteristic of HfO₂gate dielectric deposited on high mobility substrate Geusing ALD. To meet the demands of improving device channel mobility when theCMOS process technology node enter into22nm, growth of the HfO₂on high mobilityGe substrate was carried out by ALD. After a compatible annealing process forsource/drain activation for the CMOS fabrication, the different processed HfO₂filmswere investigated. The testing results show that the annealing leads to the increase ofsurface roughness, decrease of interface layer thickness and deterioration of electricalcharacteristic, especially for the H2O-based HfO₂gate structure. This is attributed to thevolatilization of GeO which is generated at GeO₂/Ge interface during the annealing, andit is demonstrated by the GeO volatilization experiment results. GeO volatilemechanism is further researched. For the H2O-based HfO₂on Ge, the adsorption-OHgroups might accelerate the GeO₂/Ge interface chemical reaction to generate GeOduring annealing, which deteriorate the HfO₂/GeO₂gate stack obviously. For theO3-based HfO₂on Ge, the O-rich film might lead to the GeO further oxidate into GeO₂,thus GeO volatilization is not significantly and the HfO₂/GeO₂gate stack show arelative good electrical characteristics.4. Improvements of the HfO₂/GeO₂gate stack electrical characteristics afterannealing using a stress relieved pre-oxide （SRPO） pretreatment. In order tounderstanding the mechanism of SRPO pretreatment, the Si substrate was pre-treated bythis method and then HfO₂films were deposited by ALD. The experiment resultsindicate that, SRPO pretreatment technology can reduce the defects in the SiOx/Siinterface layer through increasing the ratio of Si3+/Si1+.Therefore, the effect of theinterface electric dipoles in the form of Si+-O-on the electrical characteristic of HfO₂gate stack is reduced. In order to improve the thermal stability of HfO₂/GeO₂gate stack,an improved SRPO pretreatment was carried out and applied on the Ge substrate. ThenHfO₂films were deposited by ALD and annealed a compatible annealing process forsource/drain activation for the CMOS fabrication. The testing results show that SRPO pretreatment could improve the annel-induced roughness increase and electricalproperties degradation for HfO₂/GeO₂gate stack. This may be due to SRPOpretreatment increased the density of Ge4+in the interface layer, and reduced the volatilechannels of GeO volatilization. The electrical measurement results of HfO₂/GeO₂gatestack MOS capacitor show that, compared with the HfO₂/GeO₂gate stack MOScapacitor obtained by traditional RCA pretreated Ge substrate, HfO₂/GeO₂gate stackMOS capacitor obtained by SRPO pretreatment’s gate leakage current at Vg=3V isnearly1/23smaller than the former’s.