Study On The Characteristics And Deposition Processes Of High-k Gate Stack Materials

High-k gate dielectrics play a key role in the metal oxide semiconductor field effect transistor?MOSFET? and power semiconductor device. When the technology node comes to 45 nm, the equivalent thickness of the gate dielectric of MOSFET is required to be scaled to around 10?.The traditional silicon oxide gate dielectrics cannot meet the need for scaling. In order to achieve the goal of scaling down the feature size of MOSFET, the introduction of high-k dielectrics was considered to be the most promising solution. In the field of power semiconductor device, such as high-electron-mobility transistor?HEMT?, the high-k materials have also served as the gate dielectrics in order to raise the value of breakdown voltage and transconductance. La₂O₃ and Y₂O₃ high-k materials are considered as the most promising gate dielectrics in the forthcoming production. In this thesis, the characteristics and deposition processes of Al₂O₃/La₂O₃, Y₂O₃/Al₂O₃ and Y₂O₃/La₂O₃ gate stack materials are described, and the author's major contributions are outlined as follows:1. Atomic-layer-deposited?ALD? Al₂O₃/La₂O₃ gate stack dielectric structures with different La/Al deposition cycle ratio?La/Al ratio? on Al Ga N/Ga N hetero-structure epitaxy are fabricated and the characteristics of all the samples were investigated. The stable thickness and uniform surface morphology of all the samples with different La/Al ratio are observed after rapid thermal annealing by spectroscopic ellipsometry and atomic force microscopy?AFM?, respectively. The root mean squares?RMS? of all the samples' surface roughness are less than 0.47 nm. Moreover, the RMS of the surface roughness reduces as the La/Al ratio decreases. It is caused by the hygroscopicity of Al₂O₃ is weaker than that of La₂O₃. The dielectric constant of each sample obtained by using high-frequency capacitance-voltage measurement is 20, 17, 13 and 9. The dramatic drop in the dielectric of the samples as La/Al ratio decreases is caused by the formation of La?OH?3 in La₂O₃. Furthermore, the author find that with a decrease of the La/Al ratio, the dipole layer observed by X-ray photoelectron spectroscopy at Al₂O₃/La₂O₃ interfaces is close to the surface of semiconductor and the flat band voltage shifts to the negative direction. Finally, the reason for the flat band voltage shifts, which is based on the dielectric constant of Al₂O₃ and La₂O₃ comprising the position of an electric dipole layer in the dielectric films, is proposed.2. Atomic-layer-deposited Al₂O₃/La₂O₃ gate stack dielectric structures with different La/Al ratio on P-type Si substrate are fabricated. The film thickness of all the samples is nearly all the same. What's more, the RMS of all the samples' surface roughness is less than 0.65 nm. As the La/Al ratio decreases, the RMS of the surface roughness reduces and the flat band voltage shifts to the negative direction. Using the theory of dipole layer that is mentioned in Chapter 3, the reason for this phenomenon is discussed.3. The characteristic of the Y₂O₃/Al₂O₃ gate stack dielectric structures on P-type Si substrate is studied. The Y₂O₃ dielectric is fabricated by magnetron sputtering. Compared with the ALD technology, more surface damage is caused by magnetron sputtering. Using the capacitance-voltage measurement, it is found that the Atomic-layer-deposited Al₂O₃ as an interfacial layer between the Y₂O₃ film and Si substrate can remarkably raise the accumulation capacitance and make the C-V hysteresis negligible. Furthermore, after annealing, the yttrium silicate observed by XPS is formed at the interfacial layer of the sample that Y₂O₃ is directly deposited on the Si substrate. Because of the relatively low dielectric constant of yttrium silicate, the capacitance of this sample reduces and the oxide trapped charge intensity in this sample is raised. Then the intensity of interfacial traps in the samples is calculated by the conductance measurements. The result shows that there are more interfacial traps in the sample whose interfacial layer is made of Al₂O₃. In addition, the Y₂O₃/La₂O₃ gate stack dielectric structure is fabricated. Utilizing the capacitance-voltage measurement and atomic force microscopy, it was shown that, compared with the Al₂O₃/La₂O₃ gate stack dielectric, the surface morphology is more roughness and the dielectric constant of this kind of structure is relatively high. In this structure, however, the intensity of oxide trapped charge and interfacial traps is also relatively high.