Study And Realization Of8-bit PIC16F62X-Instruction-Set-Compatible MCU IP Core

The article describes the analysis and design of an8-bit MCU IP core whoseinstruction set is compatible with PIC16F62X. The designed IP core adopts the structureof Reduced Instruction Set Computer (RISC) and so it has only35format-simpleword-size-fixed instructions, which not only predigests the circuits of instructiondecoder, but also reduces the power consumption of IP core. In addition, the designed IPcore takes the advantage of Harvard architecture to separate the data bus frominstruction bus and adopts the structure of two-stage instruction pipeline which allowsall instructions to execute in a single cycle except for program branches.The article analyzes in depth the system structure, instruction set and timing toexecute the instructions and describes in detail the specific realization of the IP core.The TOP-DOWN strategy is adopted to realize the whole design. Firstly, we plan thedesign in system level and divided the whole MCU into sub-modules. Secondly wedescribe the sub-modules with Hardware Describe Language (HDL) Verilog and thewhole MCU IP core is realized by assembling all the sub-modules. At last, we validatethe IP core in two ways: one is to write test bench on EDA tool Modelsim and the otherone is to do the prototype verification taking advantage of field programmable gatearray (FPGA). The results of verification shows that the designed MCU IP core is ableto execute all the instructions accurately and the interrupt function could also runcorrectly in either normal mode or SLEEP mode.