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A novel method to identify STI quality by using gate oxide array for high density 0.13um SOC

Posted on:2004-09-25Degree:Ph.DType:Dissertation
University:The University of Texas at ArlingtonCandidate:Lee, Yuan-PiaoFull Text:PDF
GTID:1468390011974819Subject:Engineering
Abstract/Summary:
This paper reports the first time all the units for a computer were produced in one chip by “system-on-one-chip” (SOC) technology. In this case, the computer needs only the SOC chip and DRAM chips. The novel technology process was made possible by improving the quality of shallow trench isolation (STI) in SOC technology. In addition, the double Nitride/Oxide stacks innovation was applied to the STI liner layers for the first time. The result is that a computer SOC chip is going into production and on the real market for the first time. This work developed a solution for SOC technology, including identifying the STI as the source of failure mode, characterizing the failure mode, and developing the solution on Nitride/Oxide stacks.; This research has successfully developed a process for production of a high-density computer SOC chip. This computer SOC chip includes an 80X86 CPU, chip set, 3-D graphics (more than 18 Mega 6T with high-speed SRAM), audio, and others. All computer functions chips are included on this single SOC circuit.; For this computer SOC chip, the main cause of yield loss was identified as due to the STI. To increase the density of the SOC chip, the STI plays a very important role, defining and reducing the space between devices. Consequently, reducing the STI width without affecting device performance is very important.; Earlier, the STI failure mode considered being due to poor P-N junction quality, and latch-up in technologies larger than 0.25um (um = 10−6 ). For 0.13um and later generations, a new failure mode has been reported: dislocations. The STI trench is filled by the “High-Density-Plasma Chemical-Vapor-Deposition” (HDP CVD) oxide, stressing the silicon in the “active area” (AA), and inducing carriers due to silicon dislocation. Many carriers are generated by STI induced dislocation. When the electrical field is applied, the damage induced carriers impact the gate oxides of devices in SOC chip.; Thus, the gate oxide quality is affected by the STI quality quickly. According to the relationship of gate oxides quality to the STI quality, a measurement of the STI quality was developed. The development of an STI process improved STI process using a stacked Nitride/Oxide layer result in high yield of this SOC chip, a significant milestone in the history of computer chips development.
Keywords/Search Tags:SOC, STI, Computer, Oxide, First time, Gate, Failure mode
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