Real-time Imaging System Of Multi-core Computer And Optimization Of Long FFT

With the rapid development of integrated circuit manufacturing technology, the feature size is getting smaller and smaller, the degree of integration increases rapidly.NoC technology is an important technology in the ASIC design methodology, it refers to the embedded system as the core, based on IP core reuse, computer network technology and SoC technology is applied to the chip design to meet the ultra-large-scale integration circuit design, design efficiency, scalability, reusability needs.The NoC solve the bottleneck problem of the traditional bus architecture, distributed computing, storage strategy. NoC reasonable configuration of each network node is equipped with a resource type, such as the control unit, a storage unit, a dedicated algorithm processing unit, it is reasonable and efficient completion of the entire system to the desired function. NoC’s a very wide range of applications, mainly in the field of modern science and technology, communications, navigation, radar, sonar, seismic exploration, medical equipment, and radio astronomy, etc.. In just a few decades, with the extremely rapid development these systems replacement several times,. With the sharp increase in the amount of data and throughput, with a specific algorithm specialized processor in the SoC, has become an important means to improve the shape system performance.This article describes the implementation platform based on a network-on-chip multi-core heterogeneous FPGA chip. On the platform we complete the NCS algorithm development, and gives the final experimental results, including the usage of FPGA resources, the actual data processing capacity and ultimately into the quality of picture. The data through of this system reached3.65MSPS at62.5MHz frequency.After this, this paper introduced a FFT design for large amounts of data. We propose a radix-2/4/8mixed radix pipeline butterfly unit for long points FFT computation, this design can effectively reduce the computational level, thereby reducing the amount of computing while flexible support32points to4M points FFT. And for large long point FFT calculation, cooperating with DDR memory access, two-dimensional FFT calculation Radix-8algorithm design can significantly reduce the calculations of long FFT. For256K points FFT the amount of calculation can be reduced by67%. The module can complete the256K-points FFT in798639cycles.This paper studies the FFT processor SoC, dedicated to the design of high performance, low resource overhead for big points, more suitable for parallel computing FFT processor to cope with the new challenges of Big Data era in digital sign.