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The Implementation And Performance Analysis Of Hypercube In Three Dimensions Network On Chip

Posted on:2013-07-12Degree:MasterType:Thesis
Country:ChinaCandidate:X HeFull Text:PDF
GTID:2248330395485216Subject:Software engineering
Abstract/Summary:PDF Full Text Request
With the development of semiconductor technology and the decrease in featuresize of electronic components, more and more intellectual property (IP) cores can beintegrated into a chip. System on chip(SoC) based on the traditional bus architecturecannot keep up with the increasing requirement of network communication. To solvethe communication bottleneck issue of SoC, a whole new idea of integrated circuit(IC)architecture named network on chip (NoC) was proposed. The core idea of NoC is totransplant the knowledge of network technology of computer into the design of chips.NoC is, somehow, similar to conventional computer network. However, NoC isimplemented in single chip, which has many limiting factors such as restricted area,power, and link length, complexity. In order to further improve the performance ofNoC, the concept of three-dimension(3D) NoC was proposed.3D packagingtechnology can shorten the communication distance between the IP cores in the chip,reduce delay, lower power consumption and improve system performance. Therefore,it has great significance to research the NoC topology which suitable for layout of3Dstructure. On the research background, this thesis mainly carries out the followingworks.Firstly, this thesis introduces five classical NoC topologies including Mesh,summarizes the topology and corresponding routing algorithm of3D Mesh and3DTorus in detail. Evaluate the network performance of2D Mesh and3D Mesh throughsimulation. Results show that3D Mesh has better performance than2D Mesh underthe same network scale.Secondly, hypercube topology has excellent features and is suitable for placingin3D structure. This thesis implements a3D NoC based on hypercube topology,which combines the advantages of3D architecture and overcomes the shortcomings ofthe hypercube placement in2D chip. The theoretical analysis shows that hypercubetopology is better than3D Mesh topology in throughput, average network delay,network diameter and power consumption, worse than3D Mesh topology in routingand chip area overhead.Finally, this thesis compares the network performance and energy consumptionof hypercube with that of3D Mesh under uniform, localized and hotspot trafficpatterns. Experimental results demonstrate that hypercube topology and3D Mesh topology have the same performance when the network has low injection rate ofpackage. With the increase of injection rate of package, hypercube topology has betterperformance than3D Mesh topology. Additionally, the average of power consumptionof hypercube topology reduced by14.7%,2.3%, and15.2%than that of3D Meshtopology under three traffic patterns respectively.
Keywords/Search Tags:network on chip, hypercube, 3D architecture, traffic pattern, performance analysis
PDF Full Text Request
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