TORUS Architecture Research On 3d Network-on-chip

Multi core architecture has been dominant in research area as well as in the market in recent years. With the increasing number of multi-core, communication becomes the hot topic. To solve this problem, it is come up with Network-on-Chip. According to the emergence of 3D IC technology, 3-Dimensional Networks-On-Chip (3D NoC) problem is becoming a hot topic.3D NoC architectures offer better performance than 2D NoC in multi-processor system. Most research results on architectures of 3D NoC focus on the 3D Mesh by now. In this paper, we design three 3D-torus topology structures(we call them as Symmetric Torus, Stacked Torus and X-Torus), under input load pattern both uniform and transpose traffic, we analyze zero-load latency and throughput of 3D Torus architectures and evaluated performance. Experimental Data from NIRGAM simulator proved that the three 3D Torus architectures showed a better overall performance than 3D Mesh under most common conditions. Specially, the performance of 3D Symmetric Torus is better than X-Torus and 3D Stacked Torus. The X-Torus is fit for uniform pattern and the 3D Stacked Torus is fit for transpose pattern.