Design Of Morse Code Process System Based On MC8051IP Core

The System On Chip (SOC) has been the best choice for the moderndigital system design. IP-based multiplexing design technique canimprove SOC’s develop efficiency and reduce the design cost, thus, itgradually becomes a mainstream design method.MORSE is the traditional wireless telegraph code that is widelyapplied in real life. The traditional method of receiving the MORSE codesignal beaten by handcraft has been out of application. Now, the methodbased on PC to realize MORSE code process lacks certain convenienceand flexibility in practical application, therefore, the research of MORSEcode process system has some practical significance and applicationvalue.The paper first introduces the description method and theimplementation ways of current digital system design and the basicconcept of SOC and IP multiplexing technique, it also studies the designflow of IP-based multiplexing design technique. Then, the paper analyzes and verifies the8bit microcontroller MC8051IP core provided byOregano Systems and combines with the features of MORSE code signaland the functions of MORSE code process system, providing the new ideaabout designing MORSE code process system based on MC8051IPcore.According the frame transmission protocol of MORSE codesynchronized serial port communication and compares with SIU forMC8051IP core. Using the Hard Description Language（VHDL）, itdesigns the MORSE serial communication submodule being completelycompatible with the control of SIU module and interface parameters,MC8051IP is redeployed, expanded and cut. MORSE serialcommunication submodule substituting SIU module is implanted intoMC8051IP core, which can generate the IP core automatically andasynchronous-serially receiving and transmiting MORSE code.In the integrated development environment of Quartus II, usingtop-down modular design method. The design fulfills the programming,design synthesis, functional verification and waveform simulation of RTL code of MORSE serial communication module and Baud Rate Generatormodule, which is integrated into the top module of IP core for MORSEcode process system. Finally, it completes the result debugging on FPGAdevelopment board of Cyclone III EP3C25F324series and realizingFPGA verification of the function of the system design.