Design And Realization Of Framing Function In HINOC Network Convergence Sublayer

With the rapid development and universal application of digital technology and network technology, the triple-network convergence of radio-television networks, telecommunication networks and computer networks has become the main trends of the development of international information technology. Countries all over the world have accelerated the process of the triple-network convergence. Research on the low-cost coaxial cable and high-speed access technology has placed a new generation major project of High-trusted Network in the Chinese high-technology Research and Development Program (863Program). HINOC (High Performance Network over Coax) technology is a new type of access technology by using the cable television channels-of-band multi-service broadband access networks. By using the existing coaxial cable television lines and distribution network, HINOC sets up the last100meters from fiber nodes to home since fiber is widely deployed and used. HINOC is a home broad-band access network communicating over exiting coaxial cable. Only adding the devices of HINOC Modem (HM), HINOC Bridge (HB) and other related equipment, HINOC can provide high-speed and high-quality access for multi-services, including IPTV, VOD, VOIP, high-speed Internet access and other broadband business applications.Combined with the application of scientific research projects "the use of cable television channels-of-band multi-service broadband access network technology research", the framing function of HINOC access network convergence sublayer is designed and implemented in this thesis which based on Faraday’s SoCreative!/MB-A320development platform. First, the HINCO access network and the MAC-layer overall design of HINOC based on FPGA are introduced in the thesis, with emphasis on the work flow and design ideas of convergence sublayer framing functions. And then the modules, which contain cyclic redundancy code (CRC) generation, framing control and split-frame control are designed. Besides the Verilog HDL code for all modules are programmed. Finally, the timing simulation of each module is carried out with the Xilinx ISE development environment and ModelSim SE, which verifies the correctness of the program. Moreover, the FPGA design is completed and the framing function of HINOC access network convergence sublayer is realized.