Design And Simulation Of Passive Radar Signal Processing Module Based On ICS554

As the key component of passive radar signal processing system, this paperdescribes the hardware functions and operating modes of the high-speed acquisitioncard ICS554first, and highlights the characteristics of the FPGA module and itsresources. And then the basic principles of the FIR and FFT are introduced. Arealization of the two signal processor hardware programs is presented which is chippedwith the characteristics of the FPGA, and based on a modular design, The innovation inthis paper is the subject of the FIR digital filter coefficients with SD encoding, andprocessing on the FFT butterfly operator. The Verilog HDL code is written andsynthesized in ISE, and the design is verified and simulated by the ISE’s integratedsimulator. Compared with the traditional signal processor, the design in this paper hasthe advantages of good flexibility, easy expansion, high speed processing, goodreal-time, small footprint, and so on.