DDR SDRAM Interface Design And Static Timing Analysis

As of DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is widely applied to embedded SoC (Systems on a Chip), It has become popular to the DDR SDRAM controller interface design and timing closure. One hand, with the rapid development of the multi-function and high performance chip, it is getting higher and higher to clock frequency requirements of primary storage device for the entire system, also put higher requirements for the storage and processing of large data streams, so what kind of data path design is undoubtedly one of focus on the DDR SDRAM interface design. On the other hand, with the fast growth of integrated circuits, carrying out the overall successful STA (Static Timing Analysis) for chip is a key to ensure that it can work. Especially entering the era of deep submicron chip design, the effects of signal integrity and on chip variation have been considered in STA. The double data rate of DDR SDRAM brings a new challenge in interface timing closure. It is very important to successfully perform STA for the overall chip, which will make sure that the chip is able to meet functional and performance requirements.This paper presented a DDR SDRAM controller interface design of a90-nanometer mobile baseband chip. Base on system functional and peformance requirements, the chip was integrated an Infineon156MHz DDR SDRAM. By studying and analyzing interface signals and read-write transaction, it has been understood to interface characteristics and timing requirements of the DDR SDRAM, its controller unique design structure of clock signal (CK/CK_N), DQS (data strobe signal), DLL (Delay Lock Loop) and read-write data path. Finally came to a conclusion of the key timing characteristics of the DDR SDRAM controller. At the same time, the timing closure was performed by a system level timing analysis approach--internal path approach with Synopsys PrimeTime. The paper described the detailed interface timing constraints and DDR SDRAM STAMP model setup; also there were some special timing treatments for the unique interface signals and data paths. Especially took consideration of effect of PCB wiring, packaging and external loading. Internal path approach is an efficient, accurate, intuitive and comprehensive to perform timing closure for memory controller interface, and it is also worth learning during the timing analysis of similar controller interface.