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Research And Design Of Class S Power Amplifier

Posted on:2014-04-05Degree:MasterType:Thesis
Country:ChinaCandidate:Z W MaFull Text:PDF
GTID:2208330434472453Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
In recently several years, portable communication equipment have been developed rapidly and meanwhile wireless communication technology move towards to LTE and4G gradually, which puts more strict demand on communication chip. Low power, small area, wide bandwidth, multi-mode and high data rate have become trend of future. Compared with other PAs, high efficiency, low power and high integration Class-S PAs are more attractive which are put forward lately. The Class-S PA is an integration of all digital RF signal generator and switch mode PA.All digital RF signal generator transfers the baseband signal into modulated digital-RF signal, including multistage FIR interpolation filters, digital mixer, high speed ΔΣ modulator and up-sampler. Interpolation filters are used to increase the sampling frequency and remove the image-frequency, digital mixer up-converts the signal of low frequency to intermediate frequency, band-pass ΔΣ modulator converts multi-bits signal to single bit and up-sampler shift the signal of intermediate to radio frequency. With the rapid development of process, designing digital circuits operating on several GHz becomes possible. By comparison with analog and RF circuits, digital circuit has advantages in aspects of noise tolerance, system stability and low power. The ΔΣ modulation only needs hard shift, addition and storing, which is simple and implemented easily contrast to other digital modulations. In addition, the thesis presents the technique of depression coefficient quantization and optimization method of multiplying by coefficient simultaneously, also recommends high speed ΔΣ modulator architecture and optimization of noise transfer function. The chip is manufactured in TSMC65nm GP process and occupies lxlmm2.When inputting single tone sine wave and modulator operating at the frequency of1.392GHz, the SNR is52.28dB in the20MHz band-of-interest and the chip consumes32.5mW with the power voltage reaches1.1V. WCDMA signal is sent to the chip operating at the same frequency, the ACPR of band-of-interest are47.99dB,37.56dB,38.07dB,47.38dB at-10MHz,-5MHz,5MHz and10MHz, respectively and the power is31m W only.After comparison with other common switch mode PA, the current mode Class-D PA is preferred and the paper discussed the factors affect the output power and efficiency of Class-S PA are discussed. The efficiency of widely used linear PA is only10~20%and switch mode PA can be close to50%that is a big rise. But the test result is far from ideal value and band-pass waveform is seen only when digital power voltage is very high. More dedicated design is needed.
Keywords/Search Tags:Class-S power amplifier, FIR filter, high speed band-pass△∑modulator, digital mixer, current mode Class-D power amplifier
PDF Full Text Request
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