The Research And Design Of CMOS Integrated Temperature Sensor

In this paper, the developing history, present situation and trends of temperature sensor and CMOS integrated temperature sensor were summarized. The dominance and properties of the CMOS integrated temperature sensor were also described, and the research meaning was pointed out. The temperature related model and the influencing factor of two temperature sensing devices, subthreshold MOSFET and PNP substrate transistor, based on CMOS process were analyzed and compared, and pointed out that the PNP substrate transistor was more fit for being the temperature sensing device. According to the comparison of the types of the CMOS integrated temperature sensors, and combine with the properties of Σ-Δ converter type and duty-cycle-modulated type, a new framework of low power consumption CMOS temperature sensor was presented. The temperature sensing circuit, one order Σ-Δ modulator and digital low pass filter were designed. The current-output mode was adopted in the temperature sensing circuit. According to the theory of the bandgap reference, A PTAT current generator was designed, and the PTAT current was as the initial signal which related to the temperature. The traditional bandgap reference circuit was improved in the design, which includes the applying of self-bias structure and cascode structure. By using the improvement method, we obtained low power consumption, high linear and high PSRR PTAT current generator, which in a simple circuit structure. The Σ-Δ modulator was also improved against the current input signal mode. It was designed incorporated with the forestage bandgap circuit. The self-bias of the bandgap circuit was used as the bias of the two stage comparator. The comparator's open loop gain was over 100dB, and it also has low power and high sensitivity. The voltage reference generator was the expansion of the bandgap circuit for saving the resources. The nonlinear output of the modulator was calibrated by using the aid of the Matlab, and obtained a group of subsection linear equations. The digital low pass filter circuits was simplified designed. A 13 bit asynchronism counter with the function of reset and latch was designed as core of the filter circuit. The resolution and the SNR of the ADC we designed were reach to 10 bit and 51dB respectively. A narrow-pulse-generator was added in the circuits, this made the counter reset itself in the every begin count. The CSMC 0.6 u m process model library was choice for design. And the Cadence Spectre simulator was used for the circuits' simulation and test. The results displayed that the minimum accuracy of the...