Research On Sub-network Partition And Broadcast Mechanism For Reconfigurable Many-core Processor

The Many-core processor based on the Network-on-Chip (NoC)interconnect structure has a large number of computing resources, ahigh-performance parallel processing capabilities, which is the futuredevelopment trend of microprocessor architecture. With the increasing ofthe number of cores in a chip, how to effectively make use of the largenumber of computing resources, and improve system throughput havebecome an important problem facing by Many-core processor architecture.Meanwhile, as the number of processor cores and complexity of on-chipnetwork increases, the Cache Coherence Wall will restrict Cacheperformance improvements.Merging the local number of processing units into a VCG (VirtualComputing Group) can effectively improve the utilization of computingresources. Oriented to network-on-chip, take the strategy of sub-networkpartition, which will arrive path isolation between different sub-networks,in favor of the implementation of Cache Coherence, and reduce theoverhead of the Cache Coherence greatly by limiting the communication inthe sub-network instead of the whole network. This paper presents theconcept of Logic Sub-network and Phys ical Sub-network, which the formerone guarantees effective logical isolation between sub-networks, and thelatter one ensures correct communication routing achieved in sub-network.Compared with previous studies, this approach enhances the degree offreedom of sub-network partition greatly. At the same time, some specificCache coherence protocol have a large number of broadcast communicationcharacteristics, the broadcast mechanism based on tree-based XY routing can effectively reduce the power consumption and communication delayoverhead of network-on-chip broadcast communication.This paper based on Gem5multicore simulation platforms, realized aXY routing broadcast mechanism based on sub-network partition. Theexperimental results show that, compared to Unicast-based broadcastmechanism, network-on-chip performance has been greatly improved.