Optimizing The Improvement Of The Copper Seed Layer For Electroplating Copper Hole Defects

With the downscaling of the semiconductor devices, backend interconnection plays a more and more important role for the density, speed, power and reliability of the chip. The improvement of interconnect material and interconnect technology became a key point of the progress of semiconducting manufacture technology. The Cu line to instead of the Al line is the obvious s landmark of the improvement. Using Low K material, example FSG, the delay that caused by the metal line has been reduced to a acceptable level. But we also have to face some Cu line issues, such as the reliability with Cu and low K dielectric, and post-CMP (Chemical Mechanical Polishing) Cu line voids defect.In this thesis, by studying the mechanism of Cu metal line voids defect. And based on this, the process is optimized by a series of comparison experiment. Comparing the Cu void performance with Cu seed film processed by different PVD Sputter equipments, And also we compared the performance after fine tuning some process key parameters, such as sputter power. And more, the Cu void performance comparison of different plating rotation speeds. Finally we found the optimal process conditions, which can improve the defects by several process conditions. Considering the cost and benefit of mass production, we selected the low rotation speed ECP process as the final condition. It can significantly reduce the defects and improve yield and reliability of products.