The Chip Failure Analysis And Solution Caused By Crystal Lattice Dislocation Based On0.18um Technology Process

Currently, many kinds of electronic product created, such as the cellphone with the better performance, the more convenience Laptop. Amongthese continuously updated products, semiconductor plays a remarkablerole. And the product high yield also is the key factor in the semiconductorindustry.In the paper, the research has been done about how to improve yieldfor a power management IC based on0.18um CMOS logic process.Because the process is mature, forecast it will get a good yield result. Butthe first lot, yield is only19%. The most failure item is IDD off which isrelated to source drain off current..To find out the root cause and improve yield, the paper discuss how touse failure analysis method and right experiment to achieve to a high yield.Firstly, do failure analyses for the failure chip, much crystal latticedislocation was found in the active area. Secondly, after confirmed theexperiment result and did analysis, the thick gate oxide deposition methodwill be changed from wet gate oxide deposition to dry gate oxidedeposition. And the dislocation was eliminated, Idd off was low andincreased the yield.From the paper, it indicate that even the0.18um CMOS process ismature, but the similar process will get failure for their slight difference,the product specialty need to be noticed to achieve to a high yield.