Design And Optimization Of Key Load Store Technology In High Performance Processor

With semiconductor technology and computer architecturedevelopments, speed gap between high performance processor andmemory system becomes even more obvious, constraining processorfurther development. From the perspective of instruction execution, tosolve storage wall problem is to increase data load and store efficiency.Taking load and store queue as breakthrough, this paper conducts researchand design on key data load and store technologies in high performanceprocessor.After studying load store queue and optimization methods in highperformance processor, this paper introduces ESVW design scheme, basedon load instruction re-execution and Store Vulnerability Window methods.ESVW makes full use of load and store data locality, further reducesmemory access rate. Based on the same design methodology, this paperintroduces queue and distribution into array processor design, suggestsarray processor architecture with load store queue and distributed cache, inorder to take full advantage of load and store data locality, to mitigate lowflexibility problem of irregular data access, and make memory bandwidthno longer performance bottleneck.RTL design, verification and logic synthesis of ESVW are achieved,analysis on timing and area is also interpreted. With SimpleScalarsimulator and SPEC benchmarks, it is verified that, ESVW can furtherreduce memory re-access rate. Compared with Store Vulnerability Window,ESVW improves system performance by about2%. In addition, RTLdesign, verification and logic synthesis of array processor are also finished, algorithms like DCT, FFT and FIR are used to evaluate performance. It isindicated that load store queue can improve system performance by about5%, at the cost of4.7%chip area increase.