Design And Implementation Of Control Path In High Definition Frame Rate Conversion System

With the development of high definition digital TV, the improvement ofvideo quality leads to a great scale of data. In order to reduce transitionbandwidth, the best way is to compress input video frequency. Meanwhile,the refresh rate of current display is far more than frequency of video. What’smore, the characteristic of liquid crystal leads to a result that when LCDdisplays video of low frame rate, ghosting or motion blur phenomenon wouldhappen. Therefore, the frame rate conversion technology used in HD videoscan solve these problems very well, and improve the video quality efficiently.At beginning, this paper introduces the frame rate conversion algorithmbased on3DRS, and gives the overall hardware architecture. In this design,the key part is to control the data flow of system, so that can process the largescale of data as fast as possible. This paper focuses on the designing of thecontrol path in frame rate conversion system. First paper designs the overallpipeline structure, and arranges pipeline modules in a reasonable way. Thismethod helps to control the processing time of different modules, andminimizes null cycles of the pipeline. Since there existing data dependenciesamong surrounding pixels or vectors, a block-based method is used to reducethis kind of dependencies, and to increase system’s parallel level. Secondaccording to the features of pixel cache, paper designs a reusable requestingway to pixel cache, improves the efficiency of pixel cache. Last, paperproposes system data flow, and implements control path in block sequencer,as well as optimizes its key module, improve its capability.Then this paper designs overall verification scheme of the system, andfinishes synthesizing, simulation and verification of control path in the system. IMC software is used to examine code coverage of block sequencer,and the result shows that almost each module has a coverage of more than95%, which guarantees completeness of block sequencer. Also this paper usesRC software to synthesize block sequencer, which has an area of145184um~2in65nmCMOS. The results demonstrate that design can fulfill therequirement, which is, converting input video from1080P@60Hz to1080P@240Hz under main frequency of200MHz.At last, based on the HD frame rate conversion system, the UHD framerate conversion system architecture is proposed. In order to meet higher datademand, this design presents algorithm optimization on both block size andsearching region, and architecture optimization on pixel cache. Besides,aiming at the problem of cycles insufficiency, a serious of methods areproposed, such as handshake signals optimization and motion vectorsreduction, which can solve the problem effectively, and meet the frequencyrequirement, more important pave the way for the implementation of UHDframe rate conversion system.