Design And Implement Of Digital Video Post-Processing Chip

For the past few years, with the rapid development of multimediacommunication technology and very large scale integrated circuit, the dominantposition of the analog television system is gradually replaced by digital televisionsystem. At present, video signal receiving terminals in the field of familyentertainment, security, automotive entertainment and mobile communicationemerge one after another, and in the general case a display terminal can not supportall the video formats, which makes video post-processing chip is becomingincreasingly important in the field of video signal processing, the market of videopost-processing chip is more and more big, however, we have few technologyaccumulation in video post-processing chip, our technology develops slowly. Wemust master the key technology of video post-processing chip in order to break themonopoly position of the foreign video chip giants(such as Philips Semiconductors,PixelWorks). The design and implement of a high performance video post-processing chip of our own is imminent.The working principle of video post-processing is introduced in this thesis,including image enhancement, video scaling, scan rate conversion, video mixingand so on. The main contribution of this paper is that it discusses the video scalingsystem and on screen display system, and the ASIC implement of this two systemare both proposed. A video post-processing chip in which this OSD system isintegrated has taped out successfully in the180nm COMS process of UMC.In the scaling system, a nonlinear adaptive interpolation system is used toscale the luminance(Y) component, and normal bilinear interpolation is applied forchrominance(U and V) components, the interpolation algorithms for luminancecomponent and chrominance components are different because the human visualsystem is not very sensitive to the chrominance components while very sensitive tothe luminance component, The circuit structure is proposed based on the algorithm，Verilog HDL is used to describe the circuit and the design is synthesised into anetlist of gates. The OSD system has many useful functions and register resourcewhich can be programmed by software. A improved SRAM character matrix storagestructure which can greatly improve the SRAM utilization ratio is proposed, itmakes limited SRAM resource can accommodate more characters. This thesis gives the working principle of the OSD system, detailedly explain the matrix storagestructure in SRAM, the matrix index method and principles of some importantcharacter attributes. This OSD system has been verified on FPGA of Xilinx and theresult picture is presented.Finally, this article put forward some future work, hoping a better scalingalgorithm convenient for ASIC implement can be found, OSD functions of thesystem can be consummated and the speed of the OSD system can be improved.