Soc Design And Implementation Of Key Modules For H.264Video Decoder

JVT composeded of ISO and ITU-T published H.264as new video compression standard in2003. The standard is widely used in digital TV, video communication and network streaming media. In order to improve compression efficiency, some new technologies like intra prediction and integer DCT are used in H.264. Intra prediction is an important part of the H.264decoder and there are large amount of image datas to be calculated. Decoding of transform coefficients is more frequently used in the decoding process and is one of the more time-consuming modules. It has become an important content of the research about how to employ appropriate intra prediction structure and design efficiently decoding unit of transform coefficient. The system of H.264decoder is very complex and software decoder is difficult to meet the real-time high definition decoding, so this paper uses hardware implement modules of intra prediction and decoding of transform coefficient. And then finish H.264decoder SoC system based FPGA prototype circuit board.By analyzing calculative process of the intra4x4prediction and intra8x8prediction, a general four-pixel parallel prediction unit is proposed in this paper; for intra16x16prediction and chroma prediction modes, we design reusable DC predictor and plane prediction unit. As there is no parallel prediction in intra prediction decoding process, four types of prediction share the prediction units. The utilization of hardware resources is effectively improved. In order to speed up the process of the reference pixel filtering in intra8x8prediction, this paper designs a filter structure of five-pixel parallel. According to the characteristics of four types of inverse transform in H.264decoder, the paper employ butterfly fast algorithm to design a reusable computing unit, which greatly reducing the circuit scale and improve the decoding efficiency. Finally, we complete the FPGA prototype implementation of the H.264video decoder based StarFire-V340series FPGA development board. The experimental results show that the H.264decoder realized720P30fps real-time decoding at system frequency of100MHZ.