The Research And Design Of Frequency Synthesizer In OTHR

The frequency synthesizer is a core component of OTHR. In the process of the OTHR,its radio monitoring component continues to detect the external frequencies, estimates theminimum interference frequency by the algorithm, and control the parameters of thefrequency synthesizer module to generate the the desired output frequency. Frequencysynthesizer can target the low phase noise, at the same time, the high-speedy frequencyswitching, the detailed frequency resolution, and the wide output frequency range,meanwhile, it is compatible with the digital system,and takes on the characteristics ofdigital integration and program control. Under laboratory conditions, without the radiofrequency monitoring device and calculation for minimum interference frequency, thefrequency hopping sequence is used to generate the control data of the frequencysynthesizer instead of the monitoring device.It’s presented that a frequency hopping synthesizer based on the Verilogprogram on the platform of FPGA, including the improved Gold sequence generator,the control component, the DDS and the ADPLL. In the improved Gold sequencegenerator design, the ordinary Gold status code sequence, which m sequence pairspossessing two different feedback coefficient produce, is improved on in order toobtain the improved Gold status code sequence family, which is of the bestHamming correlation performance and the greater quantity of the keyt. The controlmodule receives the different status codes from the modified Gold sequencegenerator, by hopping control parameter table, and exports the parameters of thefrequency synthesizer.The DDS, compressing the data of a cycle wave fromsampling and storing in ROM, receives the frequency control words, and then readsthe ROM data, at last, generates the frequency signal.The ADPLL, according to thepure digital characteristics, is derived from the design of the separate componentfunction to accomplish the same frequency and the fixed phase difference, andproduces efficient and stable digital domain frequency.After the testbench filesedited in Modelsim are compiled and simulated, the simulation result shows thatthe hopping rates is up to10000Hops/s and the relocking time of frequencyswitching is within5microseconds. The method can get a substantial increase inthe hopping rate and, compared to the relocking time of the analog PLL in the samefrequency band, improve it more than two orders of magnitude.