Grid Coding Modulation Cascade Space-time Block Coding In The Research And The Fpga Implementation

To date, with digitized information increased dramatically, it brings a severe test to communication system. The key points to solve the problem turn to how to improve the system’s channel capacity and transfer rate. In this paper, we mainly study the performance of a concatenated space time code. It can not only accomplish a diversity gain but also enhance the bit rate, thus it can solve the problem of limited channel capacity in communication system and realize reliable transmission with high bit rate.Trellis coded modulation (TCM) can improve the system performance without increasing the transmit power or occupying more bandwidth. Space-time block code (STBC) can obtain a wonderful diversity gain in a simple way. The concatenated code which formed by TCM and STBC owns their strengths can get both coding gain and diversity gain. The traditional concatenated code required multiple serial to parallel conversions that raised the system’s complexity. This paper proposed a new concatenated code, the code enhanced the bit rate and the error performance. At last a layered TCM-STBC system was proposed to meet the needs of future communication systems.In this paper a series of key issues of TCM-STBC system were studied:Firstly, the designs and principles of TCM, STBC, interleaving and TCM-STBC system were introduced and a simulation on TCM-STBC, STBC and SISO system was conducted. The result shows that the diversity gain of TCM-STBC is as well as STBC and TCM-STBC can obtain more coding gain than STBC.Secondly, the structure of traditional TCM-STBC code was improved and in order to enhance the bit rate and channel capacity a layered TCM-STBC system was proposed. After that a simulation of improved code and traditional code was conducted, the result shows that the improved concatenated code has a better error performance. It owns4dB better code gain at the bit error rate of10-5Thirdly, the encoding modules of the concatenated code were realized based on Altera platform and Verilog HDL. Besides, all the modules including TCM, interleaving, STBC and the concatenated code top module were simulated by Modelsim.Finally, the compilation reports between traditional system and improved system were compared. It indicates that the improved system occupied less logic resources and its timing design is more in line with the actual requirements.