Research On Rate Control Algorithm Facilitating Hardware Implementation

Rate control algorithm is the key technology of video encoder, essentiallyit is rate distortion optimization algorithm under the condition of rate constraint. Itdynamically adjusts the encoding parameters to optimize the video quality, toensure neither buffer overflow nor underflow. However, most of rate controlalgorithms are designed for software implementations, and do not take intoaccount the structure of hardware encoder and the computational complexityof rate control algorithm. The main challenges of hardware-based rate controlalgorithm implementations are complex data dependence and computationcomplexity. In response to these challenges, we optimize the structure of ratecontrol algorithm, to solve the data dependencies, to reduce the computationcomplexity and to improve the R-D performance and buffer status.In order to reduce data throughput and improve data processing efficiency,hardware encoder usually uses the Zigzag macroblock encoding sequenceinstead of the traditional raster scan order to reuse the horizontal and verticaldata in sliding window. And hardware encoder usually adopts three or fourpipe line structure in macroblock level. The combination of the two factorsresult in complex data dependence, and the validity of data which used topredict MAD in rate control algorithm is affected too. In addition, the G012rate control algorithm of H.264/AVC video coding standard using quadraticfit linear regression method to predict the MAD high complexity of thealgorithm, if implemented in hardware directly, requires a lot of gates whichis not conducive to hardware implementation. Therefore, we proposed tworate control algorithm which facilitating hardware implementation, they arerespectively efficient frame-level rate control algorithm and low-costmacorblock level rate control algorithm, both of them facilitating hardwareimplementation.The efficient frame level rate control algorithm facilitating hardwareimplementation, proposes a new structure of software and hardware division, accurate and efficient frame level MAD predicted method, macroblockquantization adaptive adjustment and low complexity mcroblock MADpredicted scheme. Rate control algorithm structure is mapped to the hardwarestructure, the frame level rate control implemented by CPU, and themacroblock level directly implemented in hardware module. Hardwaremodule and CPU module are exchanged only once per frame, the datathroughput and memory bandwidth are greatly reduced. The simulation resultshows it improve the R-D performance with0.12db and the data processingefficiency, meanwhile resolve the problem of data dependence and reducesthe computationAccording to structural characteristics of hardware encoder andcomputation complexity of rate control algorithm, this paper makes a usefulexploration to rate control algorithm facilitating hardware implementation.