The High-speed Detection Module Design Of Airborne Radar

With the development of the FPGA technology and specifical unit of digitalsignal processing integrated in the FPGA, the parallel structure with many MACcomputing unit has obvious advantages in the high-speed digital signal processing.While the DSP is only suitable for coarse-grained parallel computing, DSP isfundamentally suitable for the serial algorithm, and multi-processor system is veryexpensive. However, FPGA can achieve fine-grainedhighly parallel computingstructures in the chip.First this article describes the background of the research project and the statusof domestic and foreign, introduces the hardware structural features of the Virtex-6FPGA and discusses the principle and usage of the DSP48E1, CLB and related IPcore in detail. Because of the real-time processing requirements for high-speedsampling signal for radar detection module, the IP core of radar detection module isdesigned by the FPGA chip of Virtex-6xc6vsx315t-1ff1759. The workflow of radardetection module is which the radar signal with sampling rate of4GS/s in one road isdivided into signals with sampling rate of256MS/s by16roads. The signal withsampling rate of256MS/s completes real-time related calculation with the featurelibrary in the form of pipeline and the result is output to fllow-up module by16roadswith the strict timing points requirements of250MHz/s. This design uses the methodof rapid-related calculation to build hardware computing circuit by eight ping-pongstructure and pipelined FFT. Every two-way real number signals constitute a complexsignal and the complex signal is entered an FFT circuit. The result of FFT can beseparated two part by the relate of real part and image part to multiply with theconjugated signal of the characteristic spectrum. The IFFT result of complexmultiplication is the calculation result. In order to meet the need of processing by thesignal flowing, overlap-add method is used. This article designs the algorithmarchitecture by MATLAB and analyzes the error in the module design process. It alsoanalyzes the timing after the placement and routing of the entire module and discussesthe improvements to meet the timing requirements in design.The design of the IP core meet the consumption of the Virtex-6xc6vsx315t-1ff1759after commissioning which uses DSP48E1less than950and BlockRam lessthan65%. The IP core can operate at frequency of250MHz and the calculation error does not exceed2%. The valid data which output from the IP core also is not exceed5K clock cycles away from the valid data which input from the IP core. Finally, thearticle completes the design task.