Power Factor Correction Based On One Cycle Control Chip Design And Testing

Due to large applications of power electronics equipments in the AC power grid, current harmonic pollution is becoming more serious. It not only reduces power utilization efficiency, but also produces lots of security issues. Power factor correction (PFC) technology can effectively inhibit the current harmonics and improve power factor (PF). With the standards of reducing the current harmonics or improving power factor to enforce all over the world recent years, the PFC technology has been widespread concerned, also more and more power supply designs are using PFC.A PFC controller based on One-Cycle-Control is presented in this thesis. Also the chip has been tested. It controls the Boost converter with trailing edge modulation and mainly contains INTEGRATOR, ADDER, VEA, OUTPUT DRIVER, OSCILLATOR and error protection module like OVP, UVLO. This control method allows major reductions in component count and PCB area comparing with the traditional solutions.The controlling equations of One-Cycle-Control PFC were derived in this thesis. The sub-block design and simulation were completed, including INTEGRATOR VOLTAGE REGULATOR, VEA, and BLANKING module. The application circuit of300W PFC was designed and component parameters were calculated.The stability of voltage control loop is analyzed using Matlab. The simulation of the whole PFC circuit working in300W loading condition was completed based on CSMC1μm36V Bipolar process. With220VAC (50Hz) input voltage, the PF is0.996, and the output DC voltage is384.5V. The testing results of this PFC controller were analyzed in the last part.In this thesis, the principle of One-Cycle-Control PFC was analyzed and the design of circuits was completed with EDA softwares. Ultimately the chip has been taped out. With90VAC(50Hz) input and90W loading condition, the PF of the PFC circuit is0.9784, the efficiency is96.7%, the output DC voltage is362.5V. The theoretical feasibility has been verified.