Based On Design Systemc Mips32 Function Model

The establishment and validation of simulation model is an important part of the architecture design and verification at the processor design cycle stage. It needs to run the application program to simulation and verification. At present, most of the processor functional simulation model are implemented by C or C++language, that only a serial or multi-threaded simulation and verification is satisfied. And the late FPGA hardware prototype verification requires the use of hardware description language to design, leading to a certains of communication and duplication of work between them, and the significant inconsistencies between the different authentication model. Using the SystemC language to model, we can refine to the latter part of the hardware prototyping model on the basis of the pre-function model. It’s good to keep the consistency of architecture design model and validation model, and speed up the development process, and save design cost, as well as allow multi-core parallel simulation.In this thesis, the contents are summarized as follows:1. We make a general overview of the background and the status, and at the same time leads to the content and meaning of the thesis.2. We outline the characteristics of the SystemC language and the TLM library, especially in the areas of system-level design and verification.3. We use SystemC to design a functional model of a MIPS32instruction functional simulation model with a refined single-cycle, and also modeling a high-level storage system. And we give the rapid modeling process and the tool chain.4. We validate the model by the use of the existing test set.5. We summarize the work of the thesis and its innovation, and put forward the direction for improvement.