Implementation And Algorithm Of LDPC Codes Encoding

LDPC (Low Density Parity Check) codes is proposed by Gallager doctor in the 1962 year, which is called the Gallager code. Afterward, under Turbo code roaring success's lead, Mackay and others have restudy the LDPC codes, and discovered that it has the very good characteristic: approaches the performance of Shannon limit, easy to carry on the theoretical analysis and the research, the decoding is simple, and implement the concurrent operation. In recent years, for its outstanding performance and the form of simple and good prospects , the application of LDPC codes is increasingly favored. It will be used in B3G (Beyond 3G) and 4G, space communications, fiber-optic communications, satellite TV, mobile TV, which has become the hot research.LDPC codes belong to the linear block code which is encoded by the information sequence multiplies generator matrix.Although the check matrix of LDPC codes is sparse,the generator matrix is not.The encoding complexity of it is linearly proportional to the square of code length.The code length is very large when it be used. Also,a significant amount of memory isneeded to store their check matrices.In this way,the encoding problem of LDPC codes may be an obstacle for their applications because they have high encoding complexity.This paper mainly studies encoding problem of LDPC codes.The main goal of the paper is studied the LDPC codes encoding issue, and design the corresponding LDPC codes encoder, which support IEEE P802.11n / D2.00. The paper is commenced with the development of the channel encoding technology and the LDPC codes research's present situation, and studied LDPC codes basic concept and the decoding principle. Then, paper detailed discussed LDPC codes encoding method, including based on check matrix encoding and based on generator matrix encoding. Subsequently, paper is focused on the research of check matrix structure, including random LDPC codes structure, semi-random structure LDPC codes and quasi-cyclic structure matrix LDPC code. Finally, made use of FPGA to design LDPC codes encoder, which support IEEE P802.11n / D2.00. The paper's innovation spot is through to the LDPC codes encoding algorithm and the check matrix structure research,according to IEEE in the P802.11n /D2.00 the LDPC code's request, put forward that one new encoding method to complete the LDPC code encoding. The algorithm is linear encoding, and reduces hardware resource consumption. The paper not only achieve a multi-rate and multi-code LDPC codes encoder, but also provide the model through the earlier period FPGA design for the next step ASIC design, which is reduced the design cycle.