Research On Reconflgurable And Resisting DPA-attack Chaotic Logic Circuit

As the important carrier of information, the security of cryptographic chips directlyaffects the security of information systems, so the security of cryptographic chips is the coreof control of the security of information systems. However, the cryptographic chips whichbased on integrated circuit technology have inherent defect, that is they would leakageelectromagnetic、time、power and other important information at runtime, attackers coulduse these information such as data and data operation to crack the cryptographic chips.Side-channel attack is a new effective attacking technology against the inherent defect of thecryptographic chips. Power analysis attack is a typical side-channel attack method. It cracksthe cryptographic chips by using the power consumption information leaked fromcryptographic chips, and then gets the important information such as key of cryptographicchips.This paper does a lot of research on power analysis attack for the cryptographic chips.The main work was summarized as follow:(1) This paper presents a new chaotic logic circuit which could reconfigure and resistdifferential power analysis attack., and then uses threshold control and iteration control toachieve the chaotic logic circuit in theory which based on the chaotic unit, and then this paperdoes some verifications in turn by use of a nonlinear function, with the help of numericalsimulation software Matlab, the simulation results are theoretically proved that this chaoticlogic circuit has a good dynamic reconfiguration.(2) This paper achieves the chaotic logic circuits under Cadence full-custom IC designplatform, with SMIC.18um technology, many groups of simulation results show that thechaotic logic circuit can be dynamically reconfigured.(3) This paper accomplishes D latch design based on the chaotic logic circuit. Thesimulation results about this D latch show that the D latch based on the chaotic logic circuithas the same ability to dynamically reconfigure. Similarly, the7478complement circuitwhich composed by chaotic logic circuit also has a rich dynamic reconfiguration performance.(4) Finally, this paper uses the traditional standard CMOS logic gates and the chaoticlogic circuit in Cadence full-custom design platform to achieve eight AND gates and the core module circuit of DES algorithm, and proves that the eight AND gates and the core modulecircuit of DES algorithm constituted by the traditional standard CMOS logic gates can’t resistDPA attack, but the eight AND gates and the core module circuit of DES algorithmconstituted by the chaotic logic circuit can resist DPA attack, and the area and powerconsumption of the chaotic logic circuit smaller than the dual-rail configurable logic, so it hasa better prospect.