| This paper discusses and analyses of two traditional encryption methods, and uses the reconfiguration technology idea on the design about the implementation of cipher processing system with hardware. At the same time, by optimizing the design with FPGA technology, the paper managed to design and implement a kind of reconfigurable cipher processing system, which can effectively support diverse cryptographic algorithms and can meet the demand on system performance and flexibility. The dynamic characteristics of this reconfigurable encryption/decryption system bring great difficulties for deciphering work. So it is widely used in the field of information security. This paper makes a research on the realization technology of multiple fixed cipher reconfigurable system. And then, designs the reconfigurable system considering from the system safety, flexibility, reconfiguration aspects, combined with DES/3DES, AES password algorithm.This paper systematically discusses the realization process of the design about reconfigurable encryption/decryption system based on SOPC. First the paper introduces the research background and the reconfigurable technology research status and the research significance. Then it introduces the block cipher, especially for the realization algorithm, DES/3DES algorithm and AES algorithm, to implement the system. Next, has an introduction about the realization technology of reconfigurable system and the platform it relies on. In the end, makes a detail discussion on the design method and realization process of the encryption/decryption processing system based on the reconfigurable computing technology.The system is based on DES/3DES, AES cipher algorithm as the research object. According to the characteristics of the algorithm, designs a configuration mode which can share resource in space and configurate algorithm in time. Then it uses hardware description language Verilog HDL to realize and optimize the design, and completes a custom reconfigurable DES/3DES/AES encryption/decryption IP core. By SOPC technology, the IP core, Nios II processor, network controller and other function modules with the corresponding peripheral device is integrated to realize a hardware platform, which can have a flexible configuration of the encryption/decryption according to the specific needs. Finally programs the corresponding driver and application software, makes it become a reconfigurable encryption/decryption system.The system layout and wire on Quartus II8.0, simulation on ModelSim SE6.0, finally download to DE2for testing. The result shows that the reconfigurable encryption/decryption system can run steadily at the clock frequency of121.8MHz, which is able to meet the needs of practical application. The design hardware structure is simple, flexibility, security, which can be widely used in the field of information security. |
