Hardware Design And Implementation Of Entropy Coding And Loop Filter In AVS-s Video Encoder

In recent years, with the development of Internet of things and the promotion of peace city, video surveillance is becoming the focus of attention. The standards adopted by the main products in the filed of video surveillance of our country are MPEG4and H.264. It becomes an invisible bomb in the security field because of the high cost of patent. In such background, AVS-s, the standard for video surveillance is jointly lanuched by AVS working group and Ministry of public security. AVS-s coding structure, module of entropy coding and loop filter are studied and discussed deeply in this paper.Firstly, this paper introduces the current status of video surveillance to determine the significance of this paper. After systematic description and analysis on AVS-s standard, this paper highlights the key technologies. Then, this paper focuses on the analysis of entropy coding module, including algorithm logic and implementation of RTL. Code table switching, computing of codeword and Exponential-Golomb encoding are designed to pipeline processing unit in this module. Parallel zig-zag scan is taken to accelerate the speed of processing. At the same time, combinational logic which implements code table switching and code length determiner are taken to save the hareware resources. After a detailed analysis of AVS loop filter algorithm, a new filter order is proposed. Method of using RAM and register array to transpose and store intermediate data, reduces the memory bandwidth, accelerating the filtering speed.After the design of circuit by Verilog HDL is completed, the model of AVS-s software is researched, the author abstracts the stream required by the entropy coding module and loop filtering module. Then the input is loaded to the entropy coding module and loop filtering module. After the simulation results are obtained, the results are compared with the output of AVS-s software reference model to prove the validity of the design. Then the design is synthesized with DC and the report is got.Then formal verfication is done with Formality of Synopsys. After that, the author analyzes the capability of the design.The results of verification show that the two parts of design meet requirements of AVS-s real-time encoding.