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Research Of Lossless Data Compression Based On B-LZW Algorithm And Implementation With Hardware

Posted on:2013-06-16Degree:MasterType:Thesis
Country:ChinaCandidate:Y Y ZhangFull Text:PDF
GTID:2248330371471033Subject:Electronic Science and Technology
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With the development of science and technology, we need to face the large and complex work of data processing. The large amounts of data take up a lot of storage space and occupy lots of network bandwidth, which brings much inconvenience to the storage and transmission of information. Thus, data compression technology appears accordingly. And the lossless data compression technology spreads widely in fields such as the medical treatment, spaceflight and telecommunication and so on. The hardware implementation scheme, as a hot research direction is getting more and more attention, because of its faster speed and more powerful ability.This thesis mainly deals with the design of a lossless data compression based on B-LZW algorithm and its hardware implementation structure. We combine BWT algorithm and LZW algorithm. And we preprocess the compressing data by BWT, to enhance the correlation of data by making the identical characters cohesive and improve the compression performance.According to the algorithm, the thesis proposed a hardware structure of the lossless data compression. We realize the suffix sorting approach with the Weavesorter structure, and split the dictionary to many small dictionaries, to realize the parallel searching strategy which is suitable for hardware implementation and speeds up the searching. The whole compression structure is divided to modules realized by Verilog HDL. A hierarchical design methodology is used, to make it quite clear and concise.When choosing the division method of the dictionary, we compare the different methods to partition the dictionary and prove the validity of dictionary strategy we chosen. After the design, the compression core is simulated in ModelSim environment. And the results reveal that the hardware design can compress data correctly according to the improved B-LZW algorithm. The tool of XST is used to synthesize the codes at the target FPGA of Xilinx Virtex4XC4VSX25. The results show that it can achieve high work frequency of104.3MHz and the data processing ability is quite considerable.
Keywords/Search Tags:B-LZW algorithm, Lossless data compression, FPGA, Dictionary, Hardware implementation
PDF Full Text Request
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