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Modeling And Circuit Design Of Key Blocks In TDI CMOS Image Sensor

Posted on:2013-05-12Degree:MasterType:Thesis
Country:ChinaCandidate:C F WuFull Text:PDF
GTID:2248330362461791Subject:Microelectronics and Solid State Electronics
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Time-Delay Integration (TDI) image sensor is a particular line-array image sensor, with the repeatedly exposuring and signal integrating operating mode, high performance photo can be produced. Respect to line array image sensor, TDI image sensor is widely used in space imaging, earth observation, machine vision, document scanning et al for its high sensitivity and high signal to noise ration (SNR). This paper analysis and modeling 128 stages TDI CMOS image sensor, and the readout circuit of the TDI are designed.The operation mode and the principle of SNR increasing of TDI are analysed in this paper. Two readout method, snapshot shutter and rolling shutter and three signal accumulation method, analog domain, digital domain and mixed-mode integration are deeply analysed. The key blocks of image sensor readout circuit, including pixel array, switch, capacitor, amplifier et al with their errors are deeply researched. With the benefits of analog circuit modeling lanauage VerilogA, the pixel array, analog cumulation circuit, single slope ADC are descriped and simulated. The results verify the function of TDI image sensor.In this paper, the key boclks of digital domain accumulation of TDI are designed, includes double sampling circuit (CDS), gain programmable amplifier (PGA) and Cyclic ADC. The reset KTC noise and fixed pattern noise are cancelled by CDS circuit. The PGA module makes the sensor can work under different working condition. The Cyclic ADC is responsible for converting the ananlog signal into digital signal, and the backend digital adder complish the TDI function. The designed Cyclic ADC works two times faster than normal one by switched sampling and loading capacitors; the kickback noise of dynamic comparator by noval sample technique.The designed circuits are simulated and verified before and post layout. The designed circuits reach 60dB dynamic range, the dynamic comparacitor’s offset voltage is within 60mV, and the toal chip area is 0.09mm2, the power dissipation is 507uW.
Keywords/Search Tags:Time-Delay Integration, CMOS image sensor, Analog domain cumulation, Digital domain cumulation, VerilogA modeling, Cyclic ADC
PDF Full Text Request
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