Font Size: a A A

Area Array Ccd Image Acquisition And Signal Transmission Study

Posted on:2013-02-28Degree:MasterType:Thesis
Country:ChinaCandidate:J WoFull Text:PDF
GTID:2218330371459782Subject:Physical Electronics
Abstract/Summary:PDF Full Text Request
Based on CCD imaging chip,the technology of image acquisition and data transmission is very important in high-performance image stitching and machine vision inspection. The former can easily control the synchronization of multiple imaging chips, thus contributing to the image stitching in the high-speed movement occasions. The latter can meet a number of occasions with the special requirements of size, interface, transfer rate, such as problems of interface with the ARM. This project will design the circuit of area CCD drive and data transfer based on FPGA in order to obtain high-quality, high-resolution images which lay the foundation for subsequent image processing.The topics will select FPGA as the core devices produced by XILINX, Inc, using the hardware description language of VHDL to complete the driver of the CCD. To facilitate data storage and transmission, Analog signal,which output from CCD, should be converted to digital signal AD9824 produced by ADI, Inc. And then, digital signal which ensure the integrity of an image, will be written into SDRAM continuously and read out, by Samsung's 128Mb of SDRAM chips K4S281632K.In the back-end,using the Cypress 68013A chip, digital signal could be transfer to PC in the form of USB.68013A chip integrates the USB protocol, supporting USB2.0 and 480Mb/s which could reach the highest transmission speed theoretically.Moreover, the 68013 A's is also contain a 8051 core internal, in order to facilitate the modification of the firmware and achieve a seamless connection with the master device FPAG.In software debugging, we can use modular design. First, complete the CCD driver, configuration AD9824 register, manipulation the read and write of SDRAM, and accept and send data by USB. Then, two or three modules debug in combination. At last, all modules debug in the FBI.The final actual test results show that the system is relatively stable,and the front-end CCD exposure time can be controlled on the PC side, and the shortest exposure time is about 100us which achieve the intended purpose of the project. The system also has a good scalability and can continue to tap the new features on this basis,.For example, if the CCD reference clock can be set higher, the image will be sent more in one second,and transmitted image size can be adjusted.
Keywords/Search Tags:ICX205AL, AD9824, double RAM, SDRAM, CY7C68013, VHDL
PDF Full Text Request
Related items