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The Optimization Of The Hardware Circuits Of Duursma-Lee Algorithm

Posted on:2012-07-05Degree:MasterType:Thesis
Country:ChinaCandidate:X D WangFull Text:PDF
GTID:2218330362959246Subject:Computer software and theory
Abstract/Summary:
Bilinear pairing is a map with bilinear feature and non-degenerate feature. It is widely used in a variety of public-key cryptography schemes. Without bilinear pairing, some valuable cryptography schemes cannot be built. As time-consuming bilinear pairing calculation cannot meet application requirements, it is very meaningful to increase the speed of computing bilinear pairing. According to theoretical research in this area, the improved Duursma-Lee algorithm is the most efficient algorithm for bilinear pairing on the finite field whose character is three. Experiments show that the speed of the hardware circuit is 500 times faster than software, which means that using the hardware circuit to implement Duursma-Lee algorithm is of much value. Currently, most academic research focus on accelerating the computation, but only few academic research on reducing the circuit area is relatively little.In this paper, we propose several new methods to reduce the circuit area while not increasing the computing time of the circuit. Our methods can optimize multiplication circuit, th power circuit and cubic circuits on the finite field. And our method can be described as follows. First the circuit structure is abstracted as a specific mathematical model. Then the mathematical model is set under identity transformation. Finally, the mathematical model is turned into circuits. The methods can effectively reduce the circuit area. Thus, they are able to optimize the hardware circuits for the Duursma-Lee algorithm. Experiments show that average area of fully parallel multiplier on can be reduced by 76.2%. Average area of the partial parallel multiplier on with parallelism degree eight can be reduced by 8.9%. Average area of the cubic circuit on can be reduced by 31.7%, and the reduction is up to 87.8%. This paper also presents a method for the solution of best parallelism degree of multiplier on . This paper also present 212 recommended irreducible polynomials. Because through this study, it is found that appropriate irreducible polynomials can help one construct delicate cubic circuits. This paper can also effectively solve the problem of inadequate structural expansion of existing Duursma-Lee hardware circuits.
Keywords/Search Tags:Duursma-Lee algorithm, Tate bilinear pairing, Circuits optimization, Cubic operation in finite field, Multiplication in finite field
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