The ASIC Implement And Test Analysis Of Finite Field Polynomail Modular Mutiplier Based On FNT

Finite field multiplication is the basic arithmetic operation of many cryptosystem and coding theory. The performance of finite field multiplication is of utmost important which will influence the performance of the whole system. Time spend in cryptographic functions can be critical for the availability of services. Since the major work is to calculate a large quantity of finite field polynomial multiplication in some cryptographic systems, accelerating polynomial multiplication is valuable for these cryptographic systems.In this thesis, the design and FPGA implementation result of a finite field polynomial multiplier is presented, whose arithmetic architecture is based on the number theoretic transform. It includes system algorithm design, system architecture design, hardware architecture design, and hardware implementation and function verification. The multiplier, which has been manufactured with TSMC 0.25 μ m CMOS technology, has the character of high accuracy, high speed and low complexity. Through the chip test, the maximum clock frequency can achieve 100MHz.These works are presented in this thesis:1. A feasible architecture which can be fabricated by hardware with high speed advantages is presented in this thesis and through implemented Verilog.2. The Design Compiler of Synopsys is used here to optimize and synthesize to form a gate-level net list. Considering of test, five scan chains and RAM BIST are embedded into the system.3. Astro of Synopsys is adopt to layout. And the post simulation is supported by Star-RCXT. Static Timing Analysis is calculated by Prime Time and the result is saved in SDF file. Those files will be used in dynamic simulation by VCS.4. The chip is fabricated in TSMC by MPW. And it performs well at first tapeout.