Design And Simulation Of Buffer-Detector Based Solid State Driver

For the intrinsic characteristics of Flash Memory: erase-before-write, low speed of erase and limited erase cycles, it is impossible to use flash based SSDs directly in the file systems like HDDs. So it is necessary to design Flash Translation Layer, Garbage Collection and Wear Levelling algorithm for SSD controller. This thesis is a design of Buffer-Detector Based SSD Controller, focusing on Address Mapping and Garbage Collection algorithm.As random writes is a bottleneck of SSD performance, the thesis arises a hardware architecture named"Buffer-Detector", which can identify the sequential-locality and random-locality of data access correctly. Another important role of Buffer-Detector is to buffer data of different locality type to apply different address mapping policy. For data of sequential-locality, BDB SSD use sequential page level mapping scheme.,and addrss random data in page level mapping. To store address mapping information, the thesis adopts"Cached Mapping Addresss Table,CMT"policy. To improve random write performance, thesis arises a way of"Selective Parallel Channels Write Policy". Furthermore, we arises a policy of Garbage Collection Policy named"Three Level Collection",which is similar to Switch Merge, Partial Merge and Full Merge Operation.Through a series of simulation in different traces, we get a great improvement of write average system response time. Especially in the Financial Trace which is random writes dominant, we get an improvement of almost 20%. Besides these, we also get much less Garbage Collection Overheads and a lower write amplification(WA).