Analysis And Optimization Program For Memory Margin Test

Along with operation speed of the computer system rapidlyimproving, how to better assess the quality of the memory bus which ownsa large number of signals and complex timing become a serious problemfor motherboard vendor. This paper presented and implemented anoptimization scheme for memory margin test system, which had bettersolved the test duration, test accuracy and test scalability problems underthe existing test system.Existing memory margin test system, similar to the assessment of theDIMM, used the RSP Pro/Pro2card test all physical memory in the systemaddress space, resulting in stress test for too long. Adopting single steppingvoltage increment strategy, it can't solve the conflict between voltageadjustment number and test precision. In addition to increased margin testtime, it will lead to a bad test accuracy and stability which needs to beimproved. Current test systems only host a limited number of parallel testsbecause it was limited to COM connections between host system and testboard. Moreover, it can't achieve higher level operations such as remotecontrol and remote debugging.The optimization scheme in this paper, using boundary locationalgorithm, took the most error-prone boundary region as target test areaaccording to memory mapping. It greatly reduced the stress test time bydecreased memory test area size. Multi-stage voltage adjustment strategycombined with multi-core test not only reduced voltage adjustment numberbut also improved the test precision and stability. Network testenvironment based on TCP/IP has increased the test scalability. Experiment turns out the optimization scheme significantly improvedmemory margin testing parallelism and test time, its acceleration up to3times and5times separately, achieved the expected goals.