Research On Cache And Prefetch Based Acceleration Technology Of Embedded Flash

Embedded Flash has increasingly become an important program and data memory in microcontroller due to its advantages in cost and storage density.However,the relatively slow read speed of embedded Flash restricts the overall performance of the microcontroller,so it is very important to improve the read performance of instruction and data in Flash.Current researches mainly use cache and prefetch technology to accelerate Flash reading,but there are still two problems: 1)The cache line size is fixed,which is not conducive to adapting to various applications;2)The current prefetch technology is mainly Sequential prefetch,the accuracy rate is relatively low.Therefore,how to further optimize the cache and prefetch technology has important engineering significance for the read acceleration of embedded Flash in the microcontroller.This article first addresses the problem of low cache adaptability,and proposes a cache line size adaptive technology.During the running of the program,the hardware dynamically reconstructs the cache line size according to the observed changes in program locality,so that the cache line size changes to a better size during runtime to achieve better acceleration.Secondly,in view of the problems of waste of power consumption and high cost of missing during cache access,a way hit prediction technology is proposed,which is optimized through a combination of pre-comparison and way prediction.Thirdly,in view of the low accuracy of sequential prefetching,a stride prefetch technique is proposed to prefetch unbuffered data which is accessed in the constant step size without being affected by the step size,and avoid unnecessary prefetch of irregular access to save power.Furthermore,in response to the problem of slow reading of Flash at low clock frequency,the architecture of the Flash controller is improved to achieve continuous single-cycle reading of Flash at low clock frequency.Finally,an embedded Flash controller was designed and implemented,and integrated into the SoC system,and a verification platform was built for functional simulation and FPGA verification.Experimental results show that after adopting cache line size adaptive technology,the performance of CPU running Core Mark is improved by up to 103%;after adopting way hit prediction technology,the performance of CPU running MD5 is further improved by 2%.After adopting stride prefetch technology,the speed of DMA reading data in Flash is increased by up to 50%.The area of the controller is only increased by8%,and the power consumption is reduced by 23%.