The Design And Implementation Of Non-blocking And Miss-pipeline Global Cache On XDSP Chip

As the development of application requirements, multicore DSP has been widely applied. And the multicore architecture is becoming a research hotspot in academia. Although the speed of the processor in DSP system can increase with the rate of 60% per year, the hysteresis of the memory speed’s growth(ie, “Memory Wall”problem) has limited the upgrade of the overall performance. Global Cache is an important part of the on-chip memory system in multicore DSP. Researching on its design and optimization strategies will have great significance for relieving the performance bottleneck cased by “Memory Wall” problem.XDSP is a high performance DSP developed by NUDT.Its multiple DSP cores share the resource such as Global Cache by the ring in interconnection network, and has four DDR3 interface and plurality of IO interface.In the paper, research under the background of XDSP. Focus on then design and implement the miss-pipeline and non-blocking processing mechanism of Global Cache. The main contents include the following aspects.First of all, we describe overall of Global Cache, including the design of whole strucuture, the determination of cache mapping, the write policy of cache, the replacement policy, the chosen of memory structure and the design of control register.Secondly, we realize the miss-pipeline mechanism in the Global Cache. It makes different types of requests can parallel processing in pipeline. Through the design of efficiency input buffer, improved transmission of pipeline, reasonable judgment mechanism of conflict effectively increasing the efficiency of buffer, smoothing the data transmission between Global Cache and DDR, accelerating the efficiency for processing request.Thirdly, we design the miss request processing mechanism based on non-blocking cache. We design and optimize separately from the storage of miss request and the process of return miss data.We use miss request management support multiple relations, the deadlock solution of miss request, the co-processing between miss processing and miss buffer. It could continue the access of normal requests without stall when miss request comes. It could reduce missing-cost, ensure the high efficiency running.Finally, we conduct the verification, logic synthesis and optimization. Currently the module level verification has been completed and the function is right. System level verification is under way. We make the logic synthesis by 45 nm process. The frequency, area and power have reached the design requirements, then make the performance evaluation for the key technology.