Adapitive Radio Frequency Interference Suppression In UWB-SAR Based On FPGA

Ultra wide band synthetic aperture radar (UWB-SAR) operating at VHF/UHF band can penetrate the foliage and the earth surface to produce high resolution images of concealed targets. However, this band heavily occupied by the radio frequency interference (RFI) from television radio and wireless mobie communications. The RFI , which has the properties of time variation and space variation, may degrades the image quality greatly. Therefore, an efficient RFI surpression method is the precondition for the UWB SAR system. An adaptive filter for RFI suppression is investigated and realized in FPGA.In this thesis, the characteristics of RFI are studied at first. Then the classical methods of RFI suppression are analyzed based on the model of UWB SAR receiving signal. The approach of an adaptive line enhancer (ALE) controlled by the normalized least mean square(NLMS) algorithm is emphasized, owing to its capability to follow time variations of the signal and noise statistics. The selecting principle of prediction distance is given. Considering the failure to suppress multiple RF signals of different energy efficiently for the ALE, a cascade adaptive line enhancer (CALE) is presented with fast convergence performance and simple structure. Moreover, the problem of high side lobe level is studied and some available conclusion is provided.The ALE realized in FPGA is studied too. The structure of the NLMS algorithm is analyzed in views of the critical path and resource consume. An improved method of power accumulation can reduce M-2 (M is the filter order) multiplier blocks campred to the old method. The shift operation is adopted to substitute the division operation to reduce the computational complexity and improve the operation speed of the design. The relaxed look-ahead transform technology and retiming technology are used to cut the critical path. A pipelining transpose form retiming delay NLMS (TF-RDNLMS) structure is presented with high speed and good tracking capability, and the structure based on the real signal and complex signal are implemented by system generator. Furthermore, the latter is verified in XC4VSX55 by the hardware co-simulation.Finally, a data distribution module after RFI suppression is designed based FPGA. The receiving and transmitting modules are designed, by using a custom data header , a poll-token-based state machine is used to schedule the transmission. As a result, a network with high speed among multi-DSP is realized.