Studying Of Key Process In TSV Technology

In the last few years, Industry of integrated circuits developed very quickly. Therefore, interconnect delay plays a more important role than gate delay. Accordingly, this limits the development of IC s density. The solution is three dimension packaging technology. Among them, most popular way is Cu-interconnect technology which based through silicon via (TSV). It not only can increase density of IC, but also can reduce connected delay for its shorter connected distance.In TSV packaging technology, via etching and filling is the most important process. This process consists of four steps:via etching; insulating layer deposition; manufacture of barrier layer and seed layer; via filling. Usually, barrier layer and seed layer is deposited through PVD. These processes need two steps of sputtering and cost is high. Ordinary sputtering can't achieve good step coverage in via of high aspect ratio.Here a novel integrated process of barrier layer and seed layer was presented:Ti was prepared through magnetron sputtering. Bottom of Ti was used as barrier layer and surface of Ti was wet oxidized as seed layer. This method not only lowered cost, but also improved performance of structure.Deposited method of Cu was examed. Ion beam sputtering deposition was used during previous work. Ti we got had good continuity and electrical conductivity and was compact. However, after oxidizing, electroplating of Cu was failed for lower binding force of TiO2 and Cu. Then magnetron sputtering was adopted. Ti we got had good continuity and electrical conductivity. The difference was that roughness of TiO2 was higher than the former. This improved the binding force of TiO2 and Cu.Oxidizing process was researched. An orthogonal Experiment of three factors and three levels was designed to get better parameters.Performance of barrier layer was studied. Samples were annealed under different temperatures. Then diffusion of Cu was detected through XPS with its depth profiling.Oxidizing experiment in deep via was researched. When oxidizing experiment carried on in deep via with high aspect ratio, solution couldn't be updating in time. Oxidizing rate slowed down in via compare with that in surface of wafer. Besides, during wet oxidizing, H2 was produced and this suppressed oxidized rate in via further. Accordingly, for oxidizing Ti in surface and in via synchronously, oxidizing parameters that can lead to slow reaction were accepted. In addition, other methods were introduced:stirring, ultrasound and adding surfactant. Here special electroplating bath was introduced. They could suppress deposition rate in via opening and prevent opening of via closing prematurely. So deposition of Cu was bottom to up growth. Silicon via with aspect ratio of 2:1 was filled with void-less Cu.