Study On The Surface Roughness Of Barrier Layer Cmp And Post-CMP Cleaning For GLSI Multilevel Copper Interconnection

With the rapid development and progress of the integrated circuit technology, integrated level on chip is becoming higher, feature size is becoming smaller, and line width is also becoming more narrow, the requirement of the performance of integrated circuits is increasing, for example reduced interconnect delay, increased bandwidth, lower power consumption, lower cost and heterogeneous integration possibility. At present, internationally the feature size of gigantic scale integrated circuit(GLSI) is 22nm/20 nm which has been achieved large-scale production, the wafer of size is 300 mm, and the layer of multilayer metal interconnection up to more than 10 layers. In order to ensure the various parameters and device performance of final wafer to meet customer requirements, it requests to get better flatness of the wafer surface after each layer wiring.Chemical mechanical polishing(CMP) is recognized as a unique global planarization technology so far. While the manufacturing chemical mechanical processes required in integrated circuit planarization, barrier CMP is a key which ultimately decides the effect of the wafer CMP, and directly impacts the device performance and yield reduction. The process of barrier CMP involves the polishing of copper, tantalum, dielectric which are different property’s materials, eventually the tantalum and dielectric are completely removed, then copper lines are remaining.Due to the copper is relatively soft, after polishing,the surface appears micro-scratches, corrosion pits and other issues easily, which are the greater challenges of the barrier CMP, and the particles will adhere on the surface, these issues affect the wafer surface roughness. So the further research on the barrier CMP process and cleaning solution have very important practical significance.In this paper, the effect of polishing process parameters, polishing liquid ingredients and cleanr compositions on the copper surface roughness are explored through single factor experiments. Then the experimental data are sorted out, and the results are researched and analysed, and the final outcome of the study will be applied to the barrier CMP of 300 mm copper wiring wafer, and the surface defects of the wafer after polishing are detected. The test results are that the dishing of single copper wiring is under 450 ?, and pit is below 200 ?, and the wafer surface roughness is 0.679 nm, which meet the requirements of industrial production. The experimental results show that the alkaline barrier slurry achieve barrier feasibility layer flattening. And the alkaline slurry has the advantages of simple components, easy cleaning, environmental protection, which does not contain the traditional film corrosion inhibitor BTA, the instable oxidant composition, and also dose not exist that acidic polishing liquid lead to the problems such as corrosion, complicated composition, high cost and so on. The surface micro defect density and surface roughness of polished wafer are further reduced by cleaner, At last it obtains a good surface morphology.