A ZSP-based MP3 Decoder SOC Design

MP3 is the most popular digital audio format. Not only the MP3 player is popular, but also more and more devices need supporting MP3 function. It's the SoC technology push more and more devices supporting MP3 function. Own to the SoC technology, one side the SoC chip changed smaller and consumed less power, another side it support more and more functions. At this thesis, it will show how to use the SoC technology to design a MP3 decoder SoC. Tthis SoC is based on a soft DSP core--ZSP. ZSP is an efficient DSP which provided by VeriSilicon, Inc. ZSP is a very competive product and licensed by many famous company. So, ZSP has been applied to a wide range of areas. ZSP make this SoC more competitive and expandable.In this thesis, I introduce the MP3 encoding and decoding technology first. Then I try to get a most important optimizing method for mp3 decoding. And I try to find the best optiming method for this SoC system. The major job is software optimizing. There are 2 methods used, one is remove the redundant sector under the advance language level; and another is that optimizing the software to fullfil the ZSP architecture and making good use of the assembler. At then end, the optimized MP3 decoder SoC implemented on the FPGA board. Compare the original system with the optimized one, the results can get that the optiming method is effective. It's also a good balanced and competive SoC design when comparing this MP3 decoder SoC with the other implementation methods.