Design Of AHB Monitor Based On SHA And AES Algorithms

Information as an important tactic resource, nowadays the issue of security as an important topic has been paid a lot of attention by the designers in the security sector. The conventional solution based on software has been replaced with the total solution of SoC chip based on the security. The secure SoC processor is the core of the system where it is embedded. Therefore, its own security is very critical. By extracting the secreted information run on the SoC, different types of attacks are conducted. Therefore the advanced technology shall be implemented to protect the SoC.In the past, for the security of SoC, many papers are focused on the decryption and encryption of data instead of the protection of channel such as bus where data is transferred. Due to this reason, a new AHB monitor which senses the sequence of bus activity is introduced in this paper. The monitor is designed to prevent violated operation caused by fault injection attacks and tamper attacks.In the beginning of the paper, several applied algorithms are analyzed in aspects of theory and improved hardware realization. To fulfill the requirements of monitoring on run time, by analyzing serial CRC-16 mechanism, high speed parallel CRC-16 algorithms is implemented to avoid tedious procedures. By conducting sufficient analysis on SHA-256, number of iteration as being reduced, the new circuit of message expansion is designed to achieve high throughput of SHA-256 hardware. Scenarios on realization of AES-128 algorithms and some related techniques are analyzed. After comparing different architectures, to achieve ECB and CBC modes, cyclic repeat architecture is used to realize the AES decryption and encryption. Meanwhile, by considering the purpose of re-use, the progress of parallelism between decryption and encryption for sub program is achieved.Secondly, based on analyzing AHB specs, three already designed modules are used to design the AHB monitor assigned in the paper. By not disturbing the regular operations of AHB, the capability of monitoring is achieved. It is flexible and able to configure the monitoring algorithms. DMA is embedded to transfer a great amount of data. The overtime access is also detected by the monitor. By reusing the internal hardware resources, under non monitoring mode, the embedded SHA-256 and AES-128 algorithms can be used as regular algorithm modules. Verilog HDL is used to achieve the behavior description of the circuit. SMIC 0.13um CMOS technology is chosen to complete synthesis. As results of synthesizing, 99.2k gates are formed to the circuit. The maximum frequency is 142.5MHz for satisfying the requirements of low cost and high efficiency on SoC security chip designs.Moreover, based on AHB monitor hardware design, EDA verification and simulation are adopted to ensure accuracy in terms of timing and functionality.Lastly, the conclusion and further prospect are presented at the end of this paper. Further improvement and research direction are pointed out.